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CAT93C56, CAT93C57
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/57
will come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (t PD0 or t PD1 ).
For the CAT93C56/57, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial
SK
CS
data word is preceeded by a dummy zero bit. All subsequent
data words will follow without a dummy zero bit. The
READ instruction timing is illustrated in Figure 3.
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power ? up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C56/57 write
and erase instructions, and will prevent any accidental
writing or clearing of the device. Data can be read normally
from the device regardless of the write enable/disable status.
The EWEN and EWDS instructions timing is shown in
Figure 4.
A N
A N ? 1
A 0
Don’t Care
DI
1
1
0
t PD0
DO
HIGH ? Z
Dummy 0
D 15 . . . D 0
or
D 7 . . . D 0
Address + 1
D 15 . . . D 0
or
D 7 . . . D 0
Address + 2
D 15 . . . D 0
or
D 7 . . . D 0
Address + n
D 15 . . .
or
D 7 . . .
Figure 3. READ Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
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相关代理商/技术参数
CAT93C56XI-1.8
功能描述:电可擦除可编程只读存储器 (256x8) (128x16) 2K
RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8
CAT93C56XI-1.8-GT2E
制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM
CAT93C56XI-1.8-GT3E
制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM
CAT93C56XI-1.8T2E
制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM
CAT93C56XI-1.8T3E
制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM
CAT93C56XI-1.8TE13
制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM
CAT93C56XI-GT2
制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2-Kb Microwire Serial CMOS EEPROM
CAT93C56XI-GT2E
制造商:CATALYST 制造商全称:Catalyst Semiconductor 功能描述:2K-Bit Microwire Serial EEPROM